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- Path: news.teclink.net!usenet
- From: rad@teclink.net (rad)
- Newsgroups: comp.sys.amiga.misc
- Subject: Re: Speed: 68040 vs. 68060
- Date: 2 Mar 1996 06:35:10 GMT
- Organization: TECLink, Inc.
- Message-ID: <1195.6634T1430T809@teclink.net>
- References: <371.6633T989T2700@horus.co.jyu.fi>
- NNTP-Posting-Host: tc2_11.teclink.net
- X-Newsreader: THOR 2.22 (Amiga;TCP/IP) *UNREGISTERED*
-
- Aki Laukkanen <daeron@horus.co.jyu.fi> wrote:
- >>According to the Motorolla press release, which I could post here if
- >>anyone really gives a hoot, states the the 50MHz 060 is capable of
- >>maxing out at 250 MIPS, and averages 80 VAX MIPS.
-
- >Bollocks. Hence 68060 can execute two instrucions in a cycle at max, the 50
- >MHz model can go as high as 100 MIPS but not more.
-
- Ok, just to clear things up. Your both wrong. The 68060's limit is 2 integer
- instructions + one branch instruction per clock or 1 integer, 1 float and 1
- branch instruction per clock. That's 150MIPS peak @ 50MHz. Realistic values
- due to dependency conflicts, branch mispredictions, cache misses, etc. are
- about half that. (Ref. M68060/D p. 2) (I suppose the original post could have
- meant 250 VAX MIPS which is a different measure all together.)
-
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- - Richard Deken E-Mail: (personal) rad@teclink.net -
- - VLSI design engineer (AuE business) rad@aue.com -
- - Advanced Microelectronics PGP public key available -
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